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LOCATION:
/usr/share/microcode_ctl/ucode_with_caveats/intel-06-5e-03
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EDITING: disclaimer
Microcode revisions 0xda and higher for Intel Skylake-H/S/Xeon E3 v5 (family 6, model 94, stepping 3; CPUID 0x506e3) are disabled as they may cause system instability; the previously published revision 0xd6 is used instead. Please refer to /usr/share/doc/microcode_ctl/caveats/06-5e-03_readme and /usr/share/doc/microcode_ctl/README.caveats for details.
CANCEL
Name
Type
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↩ ..
DIR
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📁 intel-ucode/
DIR
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2026-07-31 05:36
📄 config
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80 B
2026-07-28 19:54
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📄 disclaimer
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354 B
2026-07-28 19:54
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📄 readme
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4.7 KB
2026-07-28 19:54
EDIT